In the prior art, a high frequency embedded phase lock loop (PLL) can be used to provide a fixed-frequency video clock input frequency. Additional crystals or oscillators may be required to provide the desired frequency or modify the output frequency. The input frequency is fixed. Each clock requires a separate PLL. The video frequency cannot be easily changed without impacting the entire system. PLLs consume considerable application specific integrated circuit (ASIC) real estate and crystals are expensive. Changing video frequencies may require board changes. For some applications, e.g. inline laser printing, the video frequencies must be calibrated to the print engine mechanism so board changes are not practical.
In the prior art, complicated tap-delay feedback loops are used. The delay elements require custom layout. The design requires real-time calibration to adjust for process, voltage, temperature (PVT) and PVT drift. Delay elements require complicated production testing procedures, and delay elements are not portable. A dithered input reference cannot be used and the output frequency spectrum cannot be easily smeared to reduce radio frequency interference (RFI). Due to the complex calibration and testing features, the design is large.